Prothrombin time measuring apparatus with means to start the timer in response to the initial decrement of optical transmissivity

ABSTRACT

A coagulation meter including automatic means for maintaining the test temperature at 37* C. A photocell is used to sense the change in turbidity of the contents of a cuvette. The test is started by the change in voltage output produced by the photocell when the final test component is injected into the cuvette and is ended by the change in photocell voltage output caused by the change in turbidity produced by clotting. The time between these two events is measured by a digital time circuit and display automatically actuated by a differentiation circuit and a detector circuit.

[56] References Cited UNITED STATES PATENTS Indianapolis; Lewis E. Bovard Lawrence; Larry G.

United States Patent {72] Inventors William D.Schmitz U U9 J JB BBBM 6 5 l3 3 3 7 7 m mml mn otar "8 .36 am m Sm e m wabm KuONOG 277999 666666 999999 H HH WZMWMG7 6226 7 459608 t i t t i t 27008 400 455 ,33 1 333333 0 n l M 8 YM m l w 9 a 6 L 91 $51.; h m mz bm 1 D8A B o. d N w w l n m. w mmsl a AFPA 11]] I253 2247 [iii g automatic means 7 C. A photocell is to sense the change in turbidity of the contents of a cuge output ponent is in- Primary Examiner-James W. Lawrence Assistant ExaminerT. N. Gn Att0mey-Woodard ABSTRACT: A coagulation meter includin for maintaining the test tem used vette. The test is started b produced by the photocell w jected into the cuvett digital time circuit and display ferentiation circuit and a det Indianapolis, Ind.

US WITH MEANS TO START THE TIMER IN RESPONSE TO THE INITIAL DECREMENT 01F OPTICAL TRANSMISSIVITV 8 Claims, 7 Drawing Figs. U.S. 73/64.1 23/230, 250/218, 356/39 .....GOIn 31/14, (30in 33/16 356/39; 73164.1; 250/218; 23/230 [54] rnomnonmm TIME MEASURING APPARAT PATENTED JUL 20 |97l SHEET 1 OF 4 5 F m L 2w .K R/ U mm @8 M I m WA, L mm W Sm A ma l u l mm w 09 ms Nwv E L EN 5 NNN ATTORNEYS PATENTEU JUL20 l97| SHEET 2 BF 4 N QQQ INVENTOR. WILL/HM D. SCHM/TZ gmmv 6. 062x05 LE W/S E. BOWMD ATTORNEYS PATENTED JUL20 I97l SHEET 0F 4 TEST SAMPLE PHOTOCELL T CZ/L VETTEJ\ k'os filmy/MM W %W N W m #2 w r m M M R L /:m o m mar gill m um MU N 5mm .D 0 c 0 C M w P EB m M 5 5 T F m WE W M Emmi L LR B L MM -fi E w GEE m D M W W m w. 0 MW m I m n U 7 5W '00 0T M V. 5M N P H m mm M mm L ATTORNEYS PRO'I'HROMBIN TIME MEASURING APPARATUS'WITII MEANS TO START TI-IE TIMER IN RESPONSE TO THE INITIAL DECREMENT OF OPTICAL TRANSMISSIVITY BACKGROUND OF THE INVENTION l Field of the Invention This invention relates to apparatus for measuring plasma clotting time.

2. Description of the Prior Art Various means have been used in the past for the determination of plasma clotting times. The results of such tests are particularly useful in anticoagulant therapy and in preparation for surgery. Some of the prior art equipment and procedures include timers which are started and stopped manually as well as the forming of insoluble fibrin network which will not conduct electricity. Also many of the prior art procedures require the exercise of judgment and opinion on the part of the technician running the test so that the accuracy of the test is less than might be desired.

SUMMARY OF THE INVENTION One embodiment of this invention might include apparatus for coagulation testing comprising a cuvette; means for inserting a test activating component into said cuvette; a photocell; alight source; said photocell, light source and cuvette being so arranged that a change in the characteristics of the contents of said cuvette affects the amount of light delivered to said photocell; a circuit including said photocell; means for differentiating the output of said circuit; and means for detecting an output of a given amplitude from said differentiating means.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is an electrical schematic diagram of a portion of a circuit of an apparatus embodying the present invention.

FIG. 2 is an electrical schematic diagram of a further por tion of the circuit of FIG. 1.

FIG. 3 is a schematic diagram of a gate used in the present apparatus.

FIG. 4 is a schematic diagram of a further gate used in the present apparatus.

FIG. 5 is a graph of various voltage levels throughout the apparatus shown on a time base.

FIG. 6 is a perspective view of the coagulation meter of the present invention.

FIG. 7 is a block diagram of the coagulation meter of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT DIFFERENTIATING AND DETECTING CIRCUITS Referring more particularly to the drawings and to FIG. 1, there is disclosed a photocell 10 which is connected between ground I I and a constant current source 12. The constant current source 12 includes a transistor 15 the emitter 16 of which is connected through a resistor 17 to a voltage source 20. The base 21 of transistor 15 is connected through the resistor 22 to ground 25 and is also connected to the emitter 26 of the transistor 27 the collector 30 of which is connected to the constant voltage source 20. In one specific embodiment of the invention, the various components of the constant current source have the following values:

Resistor 17 5.6 an Resistor 12 4.7 I) Transistor I5 2N4l2$ Transistor 27 2N49 I 6 Voltage source 2! 25 volts DC The function of transistor 27 is to hold the base of the transistor 15 at a constant voltage less than voltage at the constant voltage source 20. Thus the transistor 27 functions as a.

zener diode. Because the base 21 is clamped at a constant voltage, the transistor 15 conducts a constant current into its collector 30. Thus any change in the resistance of the photocell 10 produces a corresponding change in the voltage across the photocell I0. This voltage is herein referred to as e, and may be measured at the test point 31.

The voltage e is coupled to a differentiator circuit 40 through series connected resistor 41 and capacitor 42. The purpose of the circuit 40 is to differentiate the input signal so that the output at test point 41 of the differentiator circuit will be (de ldt). The differentiator circuit includes a basic operational amplifier 44 as well as dual field effect transistors 45 and 46 used to reduce the input bias current of the amplifier and further includes capacitor 47 as well as resistors 50, 50', 50" and 50". In said specific embodiment of the invention the coupling components and the components of the differentiator circuit 40 have the following values:

Resistor 4! 47 K0 Capacitor 42 I0 pf. Field effect transistor 45 2N3958 Field effect transistor 46 Resistor 50, 50', 50", 50'' I8 megll (each) Capacitor 47 0.047 pf. Operational Amplifier 44 LM709 Also components associated with the differentiator circuit have the following values:

Resistor SI 15 K0 Resistor 52 I5 KO Capacitor 55 470 pf. Capacitor 57 27 pf. Resistor 56 [.5 KO Voltage source 61 25 volts Voltage source 25 volts The field effect transistors 45 and 46 are used to reduce the input bias current of the amplifier 44. The gate 44' of the transistor 45 is coupled to the. junction 43 and receives the input signal from the photocell. The drain 60 of the transistor 45 is connected to the voltage source 61 while the source 62 of the transistor is connected to ground 65 through the resistor 51. The input terminal No. 02 of the amplifier 44 is also connected to the source 62. The input terminal No. 03 of the amplifier 44 is connected to the source 66 of the transistor 46 while the drain 67 is connected to the voltage source 61. The gate 70 of the transistor 46 is connected to an intermediate point 71 in a voltage divider 72 which includes resistors 75, 76, 77 and 80. The one end 81 of the voltage divider is connected to a constant voltage source while the other end 82 thereof is connected to ground. The amplifier 44 has its terminal No. 01 coupled to its terminal No. 08 through series connected capacitor 55 and resistor 56. Terminal No. 04 of the amplifier is connected to ground while terminal No. 07 is coupled to constant voltage source 85. Terminal No. 05 is connected through capacitor 57 to the output junction 86 of (See page 11.19 Philbrick/Nexus manual 2d edition 1968, published by Philbrick/Nexus Research of Dedham, Mass. 02026.)

to i Thus the voltage output of the differentiator at the test point 41 is e where:

(See Philbrick/Nexus Manual Same Page) (R50 Ray- R5 b 112 -l The values of C and (R,, ,+R +R +R are selected such that a signal generated by a 12.5 percent dilution of normal plasma control when reacted in the optical module will produce sutficient signal when differentiated to trigger a stop detector or detector circuit 100 which includes operational amplifier 101 and associated parts. The resistor 41 and capacitor 42 are so chosen as to reduce the frequency response of the circuit so as to provide stable operation.

Consider now a specific example to illustrate the operation of the difi'erentiator circuit. Thus e might change from l0 volts DC to l volts DC. The time constant of the differentiator circuit is:

It can be appreciated that in order to provide quick reset a reset path must be provided or else thecircuit will remain in a dynamic unbalanced state for a much longer period of time than that required to perform the test. Fast reset is provided by a field efiect transister 105. The gate 106 of the transistor is connected to a constant voltage source 107 through resistor 110. The transistor 105 has its source 107' and drain 110 in series with resistor 1 1 1 with the resistor and transistor in shunt with the parallel connected capacitor 47 and resistors 50, 50', 50", and 50". In said specific embodiment the resistor 111 has a resistance of l K0 so that when the transistor is conducting a shunt path is provided which has the following time constant:

=0.0l wconds The transistor 105 may be turned on by either of two inputs one coming from the flip-flop circuit 115 through the gates 116 and 117 and the other coming from a manual reset switch 120 (FIG. 2) through the line 121 resistor 122 and transistor 125.

Consider now the stop detector or detector circuit 100. The circuit includes the operational amplifier 101 the terminal No. 03' of which is coupled to the junction 86 through a diode 130 which is arranged to permit the flow of current through the diode 130 toward the junction 86 but to block the flow of current in a reverse direction. The circuit further includes the resistor 131 which connects the junction 86 to terminal 02' of the amplifier 101 through the emitter collector legs of transistor 132. Further components are transistor 135 the emitter of which is grounded and the collector of which is coupled to the collector of transistor 132. A resistor 136 connects the base of the transistor 135 to the junction 137. Both the operational amplifiers 44 and 101 are biased by the voltage divider 72 and associated resistors 140 and 141 as well as transistors 145, 146 and 147.

At this point it is desirable to provide a further table of component values for said specific embodiment:

Resistor 15 2.2 KG Resistor 76 2.2 Kfl Resistor 77 220 (1 Resistor 00 I0 Kfl Constant voltage source 81 25 volts Operational amplifier 101 LM709 Field effect transistor 105 2N5l63 Constant voltage source 107 +25 volts Resistor I l0 Kn Resistor 111 l In! Table -('ontinued Resistor [3| l0 K0 Resistor 122 10 KO Transistor I25 2N4 I 23 Transistor 132 2N49|6 Transistor 135 2N4l23 Resistor I40 I00 Kn Resistor 141 I00 Kn Transistor 145 2N49l6 Transistor 146 2N49l6 Transistor 147 2N49l6 With the above specific values the bias voltages at the various junctions of the voltage divider can be determined. Thus the three transistors 146, 145 and 147 function as zener diodes with the transistor 146 acting to prevent the voltage between the two bases 44 and 70 of the field effect transistors 45 and 46 from becoming so great as to prevent circuit operation. The two transistors 145 and 147 function to clamp the junction 71 at 12.5 volts. The current through the resistors 76, 77 and 80 can then be calculated to be 1.0 ma. which also determines the bias voltages at the input pin No. 03 to be 10.2 volts DC and the input pin No. 02' to be 10.0 volts DC.

The amplifier 101 has associated therewith capacitor 150 and resistor 151 arranged in series and coupled between pins No. 01 and No. 08 of the amplifier. Pin No. 07 is connected to a constant voltage source 153. Pin No. 04' is connected to ground while pin No. 05' is connected through capacitor 152 to output pin No. 06. The output of the amplifier 101 is fed through resistor 155 into the base 156 of transistor 157. The emitter 160 of the transistor is connected to ground while the collector of the transistor is connected to constant voltage source 161 by resistor 162 as well as to a junction 165 which serves as an input junction for both the flip-flop 115 and another flip-flop circuit 170. Bias resistor 171 is also provided connected between ground and the base 156 of the transistor 157. The output of the amplifier or switch 101 can be read at test point 172.

Consider now the gates and 181 (which are both and gates) which make up the flip-flop 115, the gates 182 and 185 (which are both and' gates) which make up the flip-flop 170 and the gates 116, 117 and 186. Such gates are well known in the logic art and it is sufiicient for the present description to review the effect of placing a plus signal on the various pins of the gate. In FIG. 3 a representative three terminal gate is illustrated. The following graph shows for a three-terminal gate the effect of placing a positive signal on the various terminals of the gate with a signal or no signal on other terminals of the gate. The sign 1 represents a signal while the sign 0 represents no signal In FIG. 4 a representative four-terminal gate is illustrated with the effects of placing various signals on the pins being shown in the graph below.

Pin

A l 1 I 0 O 0 0 l B 0 I 0 l 0 l 0 l C 0 0 l 0 l i 0 l D 0 0 0 0 0 0 l 0 The various gates might be provided by two commercial block boxes with a Motorola (3-3 input gate) providing the three gates 182, 185 and 186 and a Motorola (quad 2 input gate) providing the gates 116, 117, 180 and 181.

Referring now to FIG. 5, there is illustrated a graph which shows the voltage levels at various test points and at'various times throughout the operation of the apparatus. Assume now that the photocell is actuated to change its resistance from volts to volts by the injection of plasma into the cuvette. Assume further that this event occurs at 11 as marked on FIG. 5. Thus the voltage e1 at test point 31 will change abruptly from 10 volts to l5 volts as indicated in the graph. The voltage at test point 41 on the output side of the differentiator circuit will abruptly dip in a negative direction from a steady state value of 12.5 volts and will immediately return to this value. The voltage at test point 172 on the outputside of the gate 101 will also dip from its steady state value of volts DC to approximately 23.5 volts and will then return to 25 volts DC.

The transistor 157 will normally have its collector output at a voltage of zero volts because the transistor 157 will be conducting. The signal at TP 172 will turn off the transistor temporarily and cause the output to the junction 165 to rise to 5 volts. Prior to the inserting of the plasma the'output terminal 187 of the gate 180 will be at l." The output terminal 190 of the gate 181 will be at 0." The output terminal 191 of the gate 182 will be at 0 while the output terminal 192 of the gate 185 will be at a l The gate 186 will have its output terminal 193 at 0" while the gates 116 and 117 will have their output terminals at l As mentioned the junction 165 receives a 5 volt-positive signal which is a l and which drives terminal 187 to a 0" so that test point 195 goes to "0." The gate 182 also receivesthis positive signal at its center input terminal 196; however, the gate 182 output terminal 191 is at 0" and remains at 0. The change from l to 0" at 187 causes the input terminal to go from a 1" to a 0." Since input terminal 200 of gate 181 is at 0," output terminal 190 goes to a 1 ."This positive signal is delivered to the base 201 of the transistor 135 turning on the transistor and putting the junction 203 of the resistor 131 and the transistor 132 at ground potential. When the junction 203 is so maintained at ground potential, no positive output signal from the differentiator circuit can trigger the detector 100.

As explained above when so goes negativethe flip-flop 1 15 is flipped. It should be mentioned that flip-flop 115 can alsobe flipped to set position by a positive pulse from the detector. This can occur as the result of a positive differentiator output being delivered to the junction 86. .Such a positive pulse causes the pin No. 02: to go more positive'than the pin No. 03. causing the transistor 157 to turn off temporarily and to provide a signal to the flip-flop circuit in the same fashion as above described.

Referring back again to FIG. 5. the circuit is still at n. The gate 1 16 which initially has its output terminal at l" is actuated by the "1 now at thejunction 137 so that the output terminal 205 goes to 0. The gate 116 is coupled to the transistor 210 through capacitor 211 and resistor 212. The resistor 215 connects a constant voltage source 216 to the junction of the capacitor 211 and the resistor 212. The capacitor 21 1 and the resistor 215 function as a time delay and provide a decay time of approximately 8 seconds so that after this period of time the terminal 205 is returned to its initial "1 condition even through the input of the gate is at a I." At however the 0" condition of the gate is transmitted to the transistor 210 through the resistor 212. The transistor 210 has its collector 220 connected to a resistor 221 the other end of which is connected to constant voltage source 222. Because of the positive voltage normally present on the base of the transistor 210 from the voltage source 216, the transistor 210 is normally turned on and the input pin 218 to the gate 117 is normally at "0." The input goes to a l however by reason of the turning off of the transistor and the output pin 225 goes to O.1hus the voltage at test point 226 goes to 0."

This 0" condition is transmitted to the input pin 226 of the gate 186 through the linecausing the input to go to 0 and the output to go to a .1." As mentioned, the output 191 is at 0."Consequently the input terminal 230 of the gate is at 0."When the output 193 of gate 186 goes to l the input 231 also goes to 1" and the output 192 goes to 0." The out put 192 is reflected in the graph FIG. 5 at 232 which represents the test point 232 in FIG. 1. The line 233 leads away from the test point 232 into circuitry illustrated in FIG. 2. The line 233 leads to a counter 235 which includes a lighted display of the number of seconds and fraction of seconds from the'initiation of the apparatus. This apparatus is described in more detail below; however, when the line 233 is at 0" the counter counts and when the line is at 1" the counter is inhibited and does not count. Thus the counterstarts counting at 11.

The changing of the output 193 of gate 186 from "0" to l has no effect at test point 240 at :1 because the transistor 241 remains turned on thus keeping the collector 242 at ground potential through the transistor. The resistor-245 is connected to a constant voltage source 246. The base 247 of the transistor 241 is connected to resistor 250 which is connected to junction 251 to which resistor 252 and capacitor 255 are connected. Resistor 252 is coupled to constant voltage'source 256 while the capacitor 255 is connected to the output 193 of gate 186. When at t1 the voltage at the input to the capacitor goes positive, the transistor 241 is not turned off because the base voltage remains positive.

In FIG. 5 the voltage throughout the cycle is plotted for the output pin 205 of gate 116. The base 257 of the transistor 210 is alsopLotted showing that at}, the voltage drops from a value of +0.6 volts DC to a value of ET volts and then gradually returns to the +0.6 volts DC level during a period of 8 seconds through the decay of the capacitor 206 and the resistor 215. The plot 218 shows the voltage at the collector of the transistor'2l0 while the plot 225 shows the voltage at the output pin of the gate 117.

Also plotted and indicated by 260 is the voltage at the collector 260 of the transistor 261 which changes from 0 VDC to 25 volts DC at 11. This change is caused by the transmission through resistor 262 of the 0" condition at the output pin 225 of gate 117 to the base 265 of the transistor 261 which turns off the path to ground through the transistor emitter. Thus the base of the field effect transistor is raised to a plus 25 volt DC potential switching the transistor on and shorting out the transistors 270 and 271 which act as zener diodes. Thus, as explained above the circuit has a fast reset path through the capacitor 47 and resistor 111 instead of resistors 50, 50', 50" and 50". The remaining two plots on the graph are the base 247 of the transistor 241 and the collector 276 of the transistor 277.

Reference to FIG. 5 will indicate the various changes that take place throughout the cycle. Thus, during the 8 second period after t, the voltage 257 gradually increases until t2 when the transistor turnsoffand it; collector 1" whereupon the gate output pin goes to a O. The input 226 of gate 186 goes to 0" and'the output 193 goes to a l The circuit including the transistor 241 operates on the signal coming into the capacitor 255 so as to produce the signal shown in FIG. 5 at 240. It can be seen that the transistor 241 is turned off for the period beginning at I: and ending at :3 because the base of transistor 241 instantaneously goes negative outlay-t has returned to +0.6 volts DC. The positive pulse at 240 turns 65 the transistar 277 and causes its collector 276 to go to ground potential. The resistor 280 connects the collector 276 to the junction 43. Thus the turning on of transistor 277 causes a current to pass through the resistor 280. Since the resistor has a resistance of 220K, the current i2 is as follows: 44 15 This current flows out of the base-44 of the field effect transistor 45. The loss of current is sensed by the amplifier-44 which drives its output positive until the: zener diode 271 conducts through resistor 111 supplying the current :2 and thus keeping the junction 43 at practically the same potential it was before the transistor 277 fired. When the transistor turns off at I the output of the amplifier44 will be positive by an amount equal to the zener voltage of the diode 271 so that assuming the voltage at the junction 43 to be 15 volts and the zener voltage to be 6.5 volts. the voltage at test point 41 is about 21.5 volts.

This jump in voltage is shown for test point 41 in F10. 5. It is necessary for this voltage to decay exponentially through resisters 50, 50', 50 and 50" and capacitor 47. The time constant of this decay is:

l=3.38 seconds e The wave form for the decay is shown in the graph at 41. The positive values on the output of the differentiator do not fire the detector 100 for the reasons given above. In other words the diode 130 blocks any flow of positive current to input pin No. 03: of the detector 100. Also the maximum voltage on the two pins No. 02and No. 03 is controlled by the voltage at the junction 71 which is approximately 12.5 volts. The

voltage output from the differentiator does not go substantiallybelow this level until a reaction takes place in the test tube and the voltage across the photocell begins to increase substantially by reason of less light transmitted through the cuvette. This is shown in FIG. 5 as occurring at i When the voltage 2 increases the voltage at test point 41 decreases. Priorto t, the voltage at pin No. 03: of the detector has been slightly more positive than the voltage at pin No. 02:. However as the voltage goes down at the differentiator output, current flows through the diode 130 and the voltage at pin No.

"was 9.3 sr 'wb isitisfiksli ib Yl 132; 02 at which time the detector switches oti and the voltage at test point 172 drops from 25 volts DC to approximately 1.5

volts DC The transistor 157 is turned off and the voltage at its collector and at the junction 165 goes to 5 volts DC or, in other words, to a l It will be remembered that junction 137 is at l so that the input 290 is at a 1." Consequently the changing of the collector of transistor 157 from to 1 has no effect on output 187 which remains at 0." The gate 182, however, has one input 291 at 0. As mentioned above the input terminal 200 is at 0' which is also true of the input terminal 292 of the gate 182. Thus, when the input terminal 196 goes from 0" to 1,the output pin 191 goes from a 1" to a 0. The input pin 231 of the gate 185 is at 0. Consequently, when the input pin 230 goes from 1 to 0," the output pin 192 goes from 0" to l putting the test point 232 at 1 The line 233 operates the counter 235 stopping the counter at the time which is currently displaying at 1 In said specific embodiment of the invention the various above-described components have the following values:

Capacitor 150 470 pf. Resistor 151 L K Constant voltage source 153 225 Volts DC Capacitor 152 27 pt. Resistor 155 K9 Transistor 157 2N4l23 Constant voltage source I61 Volts DC Resistor 162 2.2 K11 Resistor 171 1 KO Gate 182- Glte 185} Motorola (3-3input gate) Gate 186 Gate 116 Motorola (quad 2 input gate) Gate 180 Gate 181 Transistor 210 2N4 l 24 Capacitor 21l- 47 zi'. Resistor 212 10 KO Resistor 215 270 Kn Constant voltage source 216 :5 Volts DC Resistoi 221 10 K1] Constant voltage source 222 25 Volts DC INCUBATOR CONTROL CIRCUIT The cuvette in the present apparatus is held at a constant temperature during the carrying out of the coagulation test by a circuit 401. The circuit includes a temperature sensitive thermistor 399 which measures the temperature of the incubator. The thermistor 399 is one of the legs of a bridge circuit which includes five resistors 402, 405, 406, 407 and 408. An adjustment wiper 410 is provided which makes possible adjusting the voltage at pins 2" and 3::: of amplifier 412 to be equal when the incubator block is at 37 C. If the temperature of the block deviates from 37 C., the resistance of the thermistor changes and the voltage across it changes. This voltage difference is amplified by the operational amplifier 412. The pin 1" of the amplifier is connected to a capacitor 415 which is connected through resistor 416 to pin 8" of the amplifier. The output pin 6" of the amplifieris connected through capacitor 420 to pin 8" of the amplifier. Pin 7" of the amplifier is connected to a constant voltage source 421 while pin 4" is connected to ground. Resistor 422 connects input pin 2" to output pin 6".

The amplifier 412 drives a power transistor 423 which is mounted on the incubator block. The coupling to the power transistor is by way of resistor 425, transistor 426, transistor 427, resistor 430 and transistor 431. The circuit further includes transistor 432 which has its collector connected to constant voltage source 435 and its emitter connected between the resistor 430 and the transistor 427. A constant voltage source 436 is coupled by resistor 437 to the circuit between the resistor 430 and the transistor 431. The power transistor I 423 is.located on the incubator block so that heat from the transistor heats the incubator block. A resistor 440 is located in the emitter leg 441 of the transistor 423 and connects the emitter to a constant voltage source 442. The voltage at the base 445 of the transistor controls the current through the transistor and also controls the power dissipated to the incubator block. The function of the transistors 426 and 427 is as zener diodes to provide approximately a 12.5 volt offset between the base of transistor 431 and the output pin 6" of the amplifier so as to provide proper bias conditions for the amplifier.

ln said specific embodiment the following component values are used:

Resistor 402 4.7 KG Resistor 405 2 K11 Resistor 406 4.7 KG Resistor 407 1820 X Resistor 408 10 K0 Amplifier 412 LM709 Capacitor 415 470 pf. Resistor 416 1.5 KG Capacitor 420 27 pf. Constant voltage source 42] 225 volts DC Resistor 422 l megohm Transistor 423 Resistor 425 2.2 KB Transistor 426 2N49l6 Transistor 427 2N49 l 6 Resistor 430 1 KO Transistor 431 2N3638 Transistor 432 2N49l6 Constant voltage source 435 225 volts DC Constant voltage source 436 225 volts DC Resistor 437 2.2 no Resistor 440 4.3 X Constant voltage source 442 +25 volts DC above or below 37 C Thus the operator of the device is r alerted not to use the device until the decimalpoint stops blinking; The circuit 506 which controls the blinking of the decimal point includes input line 507 which leads from FIG. 1 to FIG. 2 and connects the output of the amplifier 412 to the circuit 506. The circuit 506 further includes transistors507,

510, 511, 512 and 515 as well as resistors 516, 517, 518, 520,

521, 522, 525, 526, 527 and 528 as well as constant voltage sources 527 and 530 and ground connections 531, 532 and 533.

The transistor 515 has its collector leg 516 connected, to the filament 540 for the decimal point in the display tube 541. A regular pulse is supplied through the line 542 to the base 545 of the transistor 515 from a time base circuit 546 described below. So long as the transistor 511 is turned off, the regular pulse from the line 542 controls the transistor and causes the decimal point to blink. However, when the transistor 511 is turned on, a constant, current path is provided into the base 545 of the transistor 51S maintaining it on. When the incubator temperature is precisely 37 C., the base voltage at the base of the transistor 510 will be approximately volts DC and the base voltage at the base of the transistor 511 will be 3 volts DC. The emitter voltage of both of these transistors is set at 4 volts by means of the adjustable wiper and resistor 525. The transistor 512 serves as a zener diode and sets the junction 550 of resistors 526 and 527 at a precise voltage of approximately 6 volts. Consequently the emitters of the transistors $10 and 511 are at 4 volts.

Thus transistor 511 will be turned on and transistor 510 will be turned off and the decimal point will not blink. Assume now that the incubator temperature increases. The output-of the amplifier 412 will increase and the voltage at the junctions 520' and 521' will decrease because the transistor 507 will have a greater voltage drop across it. When the base of transistor 510 goes to a less than 4 voltage DC, the transistor 510 will turn on effectively removing the forward bias across the transistor 511 and thus turning off transistor 511. The decimal point will therefore blink until the transistor 51] is again turned on by a 37 C. temperature.

Assume now that the temperature at the incubator decreases from 37 C. The output of the. amplifier 412 will decrease so as to cause the transistor 507 to turn on more offectively and so as to cause the voltage; at the junctions 520' and 521 to increase to the point where thevoltage atthe base of transistor 511 is sufficient to turn the transistor off whereupon the decimal point again blinks. Thus only when the temperature remains at approximately 37C. will the decimal point remain on.

In said specific embodiment the following parameters and components are used:

MANUAL RESET CIRCUIT Prior to the running of a test it is necessary to. remove the numerical reading from the display and to stabilize the differentiator circuit when it is thrown out of balance by the in sorting of a cuvette into the cuvette receptacle. Because of the high time constant of the circuit, a substantial amount of time on the order of 720 seconds would otherwise be required for the circuit to stabilize. The manual reset circuit might be called a one-shot multivibrator circuit and includes the reset switch 120 located on the front of the instrumentas well as transistors 600 and 601 and gate 602 and resistors 605, 606, 607, 610 and 611. Assume the switch 120 is closed. Current flows through the resistor 607 causing; the inputterminal6l2 of gate 602 to go to a 1" and therellore causing the output terminal 615 of the gate to go to a 0." The switch 120 is connected at 616 to a 30 volt unregulated DC source. Prior to closing of the switch 120, the terminal 617 will be at 0 because the transistor 600 will be turned on. The O on the terminal 615 will be transmitted through theline 617 and capacitor 620 to the base 621 of the transistor 600 turning off the transistor until the base voltage again returns to 6 volts. Thevoltage on the base will return to 6 volts by reason of current flowing into the capacitor 620 through the resistor 605 from the constant voltage source 621. Since the resistance of resistor 605 is 50 K9 and the capacitance of capacitor 620 is 47 mfd., the time required to charge the capacitor is:

When the transistor 600 turns off, the input pin 6l7of the gate 602 goes to al, thus locking in the 0 on the output 6150f the gate 602 until the transistor ,tumson again- 8 As far as the differentiating and detecting circuits are con- .cemed, the effect of placing the 1" on the line 121 for a period of 8 seconds and then returning the lineto a 0 is to turn on the transistor for balancing the difi'erentiator circuit as above described and also to put the circuits in the starting position of FIG. 5 at t,. The 1" on the line 625 also is delivered through line 628 to the counting circuits 627 and numerical display tubes 541, 630 and 631. The effect of placing the 1" on the line 628 is to zero all of the counting circuits 627 so that they all produce zeros on the three display tubes 631, 630 and 541. The circuit from the display tubes includes a lead line 640 which returns to power supply 641. The various counting circuits and numerical display tubes are commercially available items and. might be, for example, SN7490 decade counters by National Semiconductor, SN7441 BCDto decimal decoder to driver by National Semiconductor and display tubes Model B5750 by Burroughs.

The decimal point 540 in the display tube 54 l is also controlled by the closing of the reset switch 120. Thus the 1 on the line 625 also is conducted to the line 632 which leads to the base 635 of the transistor 636. The collector 637 of the transistor 636 is-connected to the line 542' while the emitter 640 is connected to ground-641. The 1" on the base 635 of the transistor puts the line 542 at ground and the base 545 at ground thus turning off the'transistor 51.5 and turning off the decimal point 540 no matter whether the transistor 51 1 is turned on or not and eventhough the time base circuit 546 is putting out a pulsing output through the line 651.

Consider again the effect of the 8 second l signal "on the line 121. All of the circuits are at the voltages shown in FIG. 5

at 1 When the pulse comes in line 121 it follows line 700 to the input terminal 200 and causes the output terminal 190 to go from a l to a 0. Thus the input 290 will go from a l to a 0. The input 1 on the line 121 is also connected to the line 701 which, through the resistor 122, turns on the transistor 125. The base 265 of the transistor 261 is thereby caused to go to ground which turns off transistor 261 and causes the base 106 of the transistor 105 to go to the voltage of voltage source 107. The transistor 105 is thereby turned on causing the input and the output of the differentiator to have equal voltages. Because of the bias voltages, signal is thereby delivered to the detector circuit which puts out a signal turning on the transistor 157 and causing its collector to go to ground voltage. This places a on the junction 165. Since the gate 180 has 0 on both its inputs, it goes to l at its output 187 which also places a l on the input 197. As mentioned, the output 190 goes to 0. The gate 116 therefore goes from a O to a l at its output 205. Even so the gate 117 is not affected and continues with a l at its output and a 0" at its input because the transistor 210 remains turned on.

At the time of pressing the reset button, the signal comes in the line 121 and also travels to the input terminal 292 placing a l on that terminal. The output terminal 191, however, is already at 0." Thus, at the time of reset, tenninal 196 is at 0 and terminal 291 is at l On the gate 185, tenninals 230 and 231 are at 0 and terminal 192 is at 1 At the end of the 8 second period after closing of the reset switch 120, the transistor 600 again turns on and the input pin 617 goes to 0." The output pin 615 goes to a 1 because input pin 612 is also at 0. The base of transistor 601 receives a 1" turning on the transistor and placing a 0" on the output line 625. Thus a 0" is now placed on the line 121 and on input terminals 200 and 292 as well as on the base of the transistor 125 through the lines 700, 701 and resistor 122. The transistor 125 is turned off, the transistor 261 is turned on and the field effect transistor 105 is turned off. The change of pin 200 from 1 to 0 has no effect on output pin 190 because the pin 197 is at l Also the change of pin 292 from a l to a 0 has no effect on the output pin 191 which is at 0 because pin 291 is at l and pin 196 is at 0."

When line 625 goes from 1 to 0," line 628 does also freeing the counting circuits 627 for the counting operation. The change of the line 632 from a "l" to a 0 also turns off the transistor 636 so that the decimal point can either blink if the temperature is off or can shine continuously if the temperature is 37 C. Thus the circuit is again in readiness for the test cycle.

In said specific embodiment the following components are used:

Transistor 600 2N4 l 23 Transistor 601 2N4 I 23 Resistor 605 50 K0 Resistor 606 KO Resistor 607 K0 Resistor 610 700 1'1 Resistor 611 1 KO Voltage source 616 30 volts unregulated Capacitor 620 47 mfd. Constant voltage source 621 +5 volts Constant voltage source 626 +5 volts Transistor 636 2N4 l 23 TIME BASE AND POWER SUPPLY The time base for the digital readout is generated by dividing the 60c.p.s. line frequency by 6 resulting in one tenth of a second pulses. These pulses come into the time base circuit 546 on the input line 700. The circuitry 701 including the resistor 702, transistor 703, resistor 705, capacitor 706, resistor 707, resistor 710, transistor 711, resistor 712 and constant voltage sources 715 and 716 constitutes a Schmitt trigger and converts the incoming alternating current into a square wave direct current output which is amplified by the amplifier 720. The amplified signal is fed into a JK flip-flop 725 which is a commercial unit manufactured, for example, by Motorola under the Model No. me. 790.

As mentioned, the function of the time base circuit is to produce pulses at a rate of 10 per second. The particular illustrated circuit produces one pulse 10 milliseconds wide every milliseconds and includes the five and" gates 730, 731, 735, 732 and 736, a 3.6 volt source 737, ground connections 740, 741 and 742, 5 volt source 745, capacitors 746 and 747 and resistor 750. The various components in said specific embodiment have the following specific values:

Capacitor 746 0.0l mfd. Capacitor 747 l ml'd. Resistor 750 6.8 Kfl The output of the time base circuit is fed out through the line 651 to the gate 751 and the line 542. If the line 232 is at 0 so that line 233 is at 0, the time base pulses will be delivered to the counting circuitry 627 causing the display tubes 541, 630 and 631 to display the seconds and tenths of seconds elapsed from t, as described above. I

The power supply has been shown as a block box 759 having outputs 640, 700, 761, 760 and 762. The output 700 is an unregulated 30 volts while the output 760 is 25 volts regulated, output 761 is 5 volts regulated and output 762 is 3.6 volts regulated. These various outputs are connected where needed throughout the apparatus according to the required voltages set forth above. The power supply has a standard wall plug 765 which is connected to standard 60 cycle current for operation of the apparatus.

BLOCK DlAGRAM Referring now to FIG. 7, there is illustrated a block diagram which indicates the general operation of the present apparatus. The combination of the light source, photocell and cuvette may function as a nephelometer with the light being reflected or may function according to the change in light passing through the cuvette. The photocell is a part of a circuit the output of which is amplified and differentiated. It has been found that such differentiation helps avoid the problem caused by different test samples having different starting turbidities. Another operation which helps avoid this problem is labeled offset" in FIG. 7 and refers to the reducing of the resistance between the output and the input in FIG. 1 of the circuit diagram, in other words, the turning on of the transistor to permit the circuit to more quickly return to a dynamically balanced condition after the circuit has been tripped or started by reason of the insertion of plasma into the cuvette causing a substantial change in the resistance of the photocell.

This procedure can also be referred to as automatic leveling and it in effect zeros the chart" so that no matter what the starting turbidity is after a short period during which the sample is settling down," that is where the meter starts and also the meter is sensitive to only a substantial change in turbidity. Thus referring to FlG. 5 e can go positive or negative at l, but the device is still tripped and still automatically levels.

Also shown in FIG. 7 is a counter. The counter is automatically started into counting when the plasma is injected into the cuvette by the pipette 800 (FIG. 6). As described above, however, the automatic starting does not occur because of the injected liquid throwing a switch or the like but instead occurs because of a substantial change in the resistance of the photoelectric cell which trips the circuit and provides an accurate indication of the true starting time of the test. Of course, the end of the test occurs when clotting begins to occur and the electrical effect is always in one direction. Consequently the starting of the circuit also causes a conditioning of the circuit to not respond to negative signals and only to positive signals. This tends to prevent false readings caused by drift and settling of particles and the like. Another effect of the above describedioffset is that the circuit is not responsive at all during the first to l2 seconds of operation to any stopping signal of any amplitude this also preventing triggering prematurely by other false indicators such as settling of particles, drift and the like.

When used in the claims that follow, the term "differentiating refers to (Ax/At) as well at (ix/d!) or, in other words, taking the change in a variable over a finite period of time as well as an infinitely small period of time.

We claim:

1. Apparatus for coagulation testing comprising a cuvette; means for inserting a test activating component into said cuvette; a photocell; a light source; said photocell, light source and cuvette being so arranged that a change in the characteristics of the contents of said cuvette affects the amount of light delivered to said photocell; a circuit including said photocell; means for differentiating the output of said circuit; means for detecting an output of a given amplitude from said differentiating means; time counting means, and means for automatically starting said time counting means through said photocell and said differentiating means and said detecting means when said inserting means inserts a test activating component into said cuvette.

2. Apparatus for coagulation testing comprising a cuvette; means for inserting a test activating component into said cuvette; a photocell, a light source; said photocell, light source and cuvette being so arranged that a change in the characteristics of the contents of said cuvette affects the amount of light delivered to said photocell; a circuit including said photocell; means for differentiating the output of said circuit; means for detecting an output of a given amplitude from said differentiating means; time counting means; means for automatically starting said time counting means through said differentiating means and said detecting means when said inserting means inserts a test activating component into said cuvette; and means for automatically stopping said time counting means when said differentiating means and said detecting means detect an output of a given amplitude.

3. The apparatus of claim 2 additionally comprising means for preventing said stopping means from operating for a given period of time after said time counting means has started.

4. The apparatus of claim 2 wherein said starting means includes means for causing said starting means to be operable in response to both negative and positive starting signals of a given amplitude; and means for causing said stopping means to be responsive to a signal of only one polarity.

5. The apparatus of claim 4 additionally comprising means for preventing said stopping means from operating for a given period of time after said time counting means has started.

6. The apparatus of claim 5 additionally comprising means for maintaining said cuvette at a temperature of 37 C, and signal means for indicating when the temperature of said cuvette is at a temperatu re other than 37 C.

7. The apparatus of claim 5 additionally comprising a display for said time counting means, means for resetting said apparatus after one test in preparation for a further test, and first signal means for indicating when said resetting means is in operation.

8. The apparatus of claim 7 additionally comprising means for maintaining said cuvette at a temperature of 37 C, and further signal means for indicating when the temperature of said cuvette is at a temperature other than 37 C, said display for said time counting means being lighted, one of said signal means operable to turn at least a portion of said lighted display off and the other of said signal means operable to blink at least a portion of said lighted display. 

1. Apparatus for coagulation testing comprising a cuvette; means for inserting a test activating component into said cuvette; a photocell; a light source; said photocell, light source and cuvette being so arranged that a change in the characteristics of the contents of said cuvette affects the amount of light delivered to said photocell; a circuit including said photocell; means for differentiating the output of said circuit; means for detecting an output of a given amplitude from said differentiating means; time counting means, and means for automatically starting said time counting means through said photocell and said differentiating means and said detecting means when said inserting means inserts a test activating component into said cuvette.
 2. Apparatus for coagulation testing comprising a cuvette; means for inserting a test activating component into said cuvette; a photocell, a light source; said photocell, light source and cuvette being so arranged that a change in the characteristics of the contents of said cuvette affects the amount of light delivered to said photocell; a circuit including said photocell; means for differentiating the output of said circuit; means for detecting an output of a given amplitude from said differentiating means; time counting means; means for automatically starting said time counting means through said differentiating means and said detecting means when said inserting means inserts a test activating component into said cuvette; and means for automatically stopping said time counting means when said differentiating means and said detecting means detect an output of a given amplitude.
 3. The apparatus of claim 2 additionally comprising means for preventing said stopping means from operating for a given period of time after said time counting means has started.
 4. The apparatus of claim 2 wherein said starting means includes means for causing said starting means to be operable in response to both negative and positive starting signals of a given amplitude; and means for causing said stopping means to be responsive to a signal of only one polarity.
 5. The apparatus of claim 4 additionally comprising means for preventing said stopping means from operating for a given period of time after said time counting means has started.
 6. The apparatus of claim 5 additionally comprising means for maintaining said cuvette at a temperature of 37* C, and signal means for indicating when the temperature of said cuvette is at a temperature other than 37* C.
 7. The apparatus of claim 5 additionally comprising a display for said time counting means, means for resetting said apparatus after one test in preparation for a further test, and first signal means for indicating when said resetting means is in operation.
 8. The apparatus of claim 7 additionally comprising means for maintaining said cuvette at a temperature of 37* C, and further signal means for indicating when the temperature of said cuvette is at a temperature other than 37* C, said display for said time counting means being lighted, one of said signal means operable to turn at least a portion of said lighted display off and the other of said signal means operable to blink at least a portion of said lighted display. 